The Spring Scheduling Co-Processor: A Scheduling Accelerator

We present SSCoP, a novel VLSI scheduling accelerator for multi-processor real-time systems. The co-processor can be used for static scheduling as well as for on-line scheduling. Many diierent policies such as earliest deadline rst, highest value rst, or resource-oriented policies, for example, earliest available time rst, or their combinations can be used. When any on-line scheduling algorithm is used it is important to assess not only the speed of the scheduling itself, but also the overall performance impact of the interface of the co-processor to the host system. In this paper we describe the co-processor architecture , a CMOS implementation, an implementation of the host{co-processor interface and a study of the overall performance improvement. We show that the current VLSI chip speeds up the main portion of the scheduling operation by over three orders of magnitude. We also present an overall system improvement analysis by accounting for the operating system overheads and identify the next set of bottlenecks to improve. The scheduling co-processor includes several novel features. It is implemented as a parallel VLSI architecture for scheduling that is parameterized for diierent numbers of tasks, numbers of resources, internal wordlengths, and future IC technologies. The scheduling architecture was implemented using a single phase clocking scheme (TSPC) in several novel ways which allowed prototyping in 2 micron CMOS technology and straightforward scaling to a more aggressive .8 micron CMOS technology. The 328,000 transistor custom VLSI accelerator running with a 100Mhz clock, combined with careful hardware/software co-design results in a considerable performance improvement, thus removing a major bottleneck in real-time systems.